An important limitation in the advancement of packaging technology for higher performance in computer circuitry is the reduction of self-induced switching noise caused by inherent package inductances. This noise is generally known as Delta-I noise. Given constraints in today's multi-chip module (MCM) technology, there are nearly no degrees of freedom available for improvement in this area. Conventional noise flow in a chip can be considered in detail by reference to FIG. 1 which shows two communicating chips, "Chip 1" and "Chip 2" within a MCM. FIG. 1 shows Chip 1 utilized as a driver indicated by the Transistor T1 while Chip 2 is used as a receiver indicated by a terminating resistor, RT. A module section "module" interconnects the two chips and contains a signal line and two reference planes disposed on either side of the signal line. Two power vias disposed underneath each of the chip sites are coupled through large decoupling capacitances C10 and C11 on the board.
In operation, when the driver, Chip 1 switches on, that is T1 output goes high, current passes down the signal line to the terminator RT for the case where VC is positive with respect to GND. This current enters the GND via and travels down the module to the GND reference plane. FIG. 1 shows a fraction of the current passing back toward the sending chip while the remainder goes to the board through the decoupling capacitors C11 and back up to the Chip 2 VC reference plane. This is shown by the dotted line arrow in the righthand portion of FIG. 1.
When the VC reference plane current arrives at Chip 1, the current loop is completed by flowing through the driver. It should be noted, however, that the GND reference plane current must flow down to the board under Chip 1 and return through the VC via before it can complete its loop. This is shown in the lefthand lower portion of FIG. 1 by the dotted line arrow. When the C10 current merges with the C11 current, the board then experiences the full driver current. Also, it should be noted that even though the board capacitors are interconnected the return currents must and do flow through the reference planes in order to provide for a controlled characteristic impedance.
As shown in FIG. 1, all of the driver current must travel to the board to complete the current path. Accordingly, the effective package inductance is relatively high even in a system utilizing intramodule communication. Given the current paths of FIG. 1, a negative Delta-I noise component is introduced at the Chip 1 VC and a positive Delta-I noise component is introduced at the Chip 2 GND. When these noise components are present on the chip power supplies, they may propagate onto quiet lines potentially resulting in false switching of quiet receivers and may also disturb on chip logic gates.
Accordingly, an important consideration in reducing system susceptibility to noise is the ability to reduce the magnitude of the effective package inductance. Such a reduction produces a corresponding reduction in the magnitude of the noise component.
Given the noise current flow paths depicted in FIG. 1, one technique for reducing effective package inductance is to have the high frequency noise current circulate near the top of the module as opposed to traveling down to the board. Such a path would bypass most of the module and the board inductance. A potential technique for accomplishing this goal would be to introduce top surface module decoupling capacitors. However, within the limits of known technology, this solution is currently not feasible for use with practiced MCM techniques. Available decoupling capacitors are not compatible with existing MCM technology because excessive topside area would have to be set aside for their inclusion. This would reduce the number of chips and circuits that could be placed on the MCM significantly detracting from its overall performance and economic advantages. Furthermore, additional power planes would have to be added at the top of the MCM to provide a low inductance path between the capacitors and the chips making the module even more complex and more expensive to produce.
Therefore, an incentive remains to provide an on-chip virtual decoupling capacitor that may be synthesized within the existing chip technology.
Within the prior art, various techniques are known for suppressing positive and negative going noise pulses in chips. Noise suppression circuits are shown generally in U.S. Pat. Nos. 3,816,762 and 3,898,482. Also, integrated circuit clamping circuits are shown in U.S. Pat. Nos. 3,188,499; 3,654,530; 3,816,762; 3,898,482; 4,027,177; 4,085,432; 4,178,521; 4,216,393; 4,239,989 and 4,131,928. Those prior art patents do not deal specifically with the concept of reducing effective package inductance by rerouting the high frequency noise currents for circulation near the top of the module. Rather, they deal with circuits to suppress noise rather than attempting to eliminate the noise components per se.
Reference is made to U.S. Pat. No. 4,398,106, entitled "On-Chip Delta-I Noise Clamping Circuit" granted Aug. 9, 1983 to Evan E. Davidson et al., and of common assignee herewith. Reference is also made to the IBM Technical Disclosure Bulletin publication ".DELTA.I Suppressor" by G. E. Gersbach, Vol. 19, No. 1, June 1, 1976, page 30.